For certain transmission systems, it is necessary to derive a clock wave that is synchronized to the frequency of serial binary data bits derived in response to a received signal. In particular, such a synchronized clock wave is necessary for certain types of data detection systems and techniques.
In the prior art, it has been the general practice to employ analog techniques for providing such a result. Such techniques have frequently used so called early/late gates, wherein the energy in a first half of a received data bit is compared with the energy in the second half of the bit. The energy in each bit half is derived by analog integration circuitry. When a bit is completed, the resulting pair of integrated analog values is compared to derive an error signal having a polarity and perhaps magnitude indicative of the deviation between the energy in the two bit halves. The error signal controls the frequency and phase of a clock wave so that the clock wave is synchronzied with the data bits. The analog integration circuitry includes classical integrate/dump and sample/hold elements.
The prior art analog systems suffer from the usual problems of analog systems. Expensive components, such as precision operational amplifiers and stable capacitors, are required for high performance. A certain amount of error is introduced because of the finite time required to discharge capacitors included in the integrators. Component values change as a function of temperature and time, to reduce accuracy and performance characteristics. It is also difficult for analog circuitry to provide high performance for data signal patterns having many transitions, as well as a relatively low number of transitions. This is because the analog circuitry frequently has problems tracking high frequencies and capacitors employed in analog integrators are often incapable of holding the same charge for extensive time periods.
It is, accordingly, an object of the present invention to provide new and improved digital circuitry for synchronizing a clock wave to the frequency of serial binary data bits.
Another object of the invention is to provide a relatively inexpensive, accurate and stable apparatus for synchronizing a clock wave to the frequency of serial binary data bits.
Another object of the present invention is to provide a new and improved apparatus for synchronizing a clock wave to the frequency of serial binary data bits that are subject to frequent transitions, as well as to few transitions.